The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, as the critical dimension (CD) of a feature is scaled down, an overlay error margin is also reduced when performing a fin cut process while fabricating a fin field effect transistor (FinFET) device. The reduced overlay error margin becomes increasing difficult to manage. Accordingly, what is needed is a method for performing the fin cut process within the overlay margin error.